1. Field of the Invention
The present invention relates to a quantum device and a fabrication method thereof.
2. Description of the Prior Art
Recently, various element structures and manufacturing methods thereof have been developed in order to decrease the size of semiconductor devices. The decrease in the size of an element of a semiconductor device not only improves the degree of integration, but also generates various advantages and disadvantages of the operating characteristics of the elements.
One of the factors which controls the operating characteristics of an element is the structure of a wire through which carriers propagate. New devices have been developed to make use of quantum effects or the like of a quantum wire which makes the dimension of the electrical conduction low. For example, the increase in electronic mobility is reported by Sakaki (Jap. J. Appl. Phys. Vol. 19, No. 12. 1980, pp. L735-L738.).
In order to utilize a quantum effect, besides the requirement very small size wire which restricts the conduction of carriers to a low dimension, it is also required that the scatterings of the carriers have suppressed in order to conserve the wave property of carriers. Then, the lattice vibrations have to be suppressed by lowering the operating temperature of the element and the ionic scatterings have to be suppressed by using an intrinsic layer as a very narrow line. Further, the scatterings at the surface roughness have to be suppressed.
However, the state of the art lithography technique which makes use of an ultraviolet ray or the like has a limit of 0.5-0.25 .mu.m practically as to the processing. Further, the prior art fine processing technique utilizing dry etching cannot suppress the scatterings due to surface roughness caused by the unevenness at the surface or at the interface due to damages.
An attempt was made to manufacture a good and flat fine wire by means including not only lithography, but also crystalline anisotropy etching. For example, FIGS. 1 and 2 show quantum wires manufactured by Shimizu (Jap. J. Appl. Phys. 27, L1778-L1779 (1988)) and by Iwameji (37th Meeting of Applied Physics Association, 30a-SB-5). In FIG. 1, a silicon wire 101 having (111) side planes are formed below a protection film 102, while in FIG. 2, a silicon wire 111 having (111) silicon side planes are formed below an etching protection film 112 on a SiO.sub.2 layer 113 placed on a silicon substrate 114. These structures exceed the limit of lithography because they use crystalline anisotropy etching at silicon (111) planes and have superior flatness and linearity.
However, in the structures of the above-mentioned fine wires, the width of fine wire is limited by the length of the flat region at the top of trapezoid-like protrusions. That is, it is a problem that the structure of fine wire and the limit of the fine processing have restrictions.